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| L7200 MOZART, 12V DISK DRIVE SPINDLE & VCM, POWER & CONTROL "COMBO" PRODUCT PREVIEW GENERAL s 12V (+/- 10%) OPERATION. s REGISTER BASED ARCHITECTURE s MINIMUM EXTERNAL COMPONENTS s BCD TECHNOLOGY VCM DRIVER s 1.7A DRIVE CAPABILITY s 0.75 TOTAL BRIDGE IMPEDANCE AT 125C s LINEAR MODE s PHASE SHIFT MODULATION (PWM MODE) s INSTANTANEOUS, (GLICH FREE) SWITCH s BETWEEN THE 2 MODES. s CLASS AB OUTPUT DRIVERS s ZERO CROSSOVER DISTORSION s 14 BIT DAC DEFINE OUTPUT CURRENT s SELECTABLE TRANSCONDUCTANCE s RAMP LOADING & PARKING VOLTAGE s FULL INTERNAL VCM CALIBRATION s DYNAMIC BRAKE SPINDLE DRIVER s 2.5A DRIVE CAPABILITY s 0.75 TOTAL BRIDGE IMPEDANCE AT 125C s SMOOTHDRIVETM ARCHITECTURE s SINUSOIDAL DRIVING, VOLTAGE MODE s BIPOLAR DRIVING s BEMF, INTERNAL OR EXTERNAL, PROCESSING s SENSOR-LESS MOTOR COMMUTATION s PROGRAMMABLE COMMUTATION DELAY s FIXED FREQUENCY PWM OPERATION MODE s INTERNAL FREQUENCY LOCKED LOOP SPEED CONTROL (FLL) s PROGRAMMABLE DIGITAL FILTER FOR SPEED CONTROL LOOP s BEMF RECTIFICATION DURING RETRACT s BUILT-IN INDUCTIVE SENSING START UP s DYNAMIC & REVERSE BRAKE s BACK ROTATION DETECTION MULTIPOWER BCD TECHNOLOGY TQFP64 ORDERING NUMBER: L7200 OTHER FUNCTIONS s 12V, 5V , 3.3V AND 2.5V MONITORING WITH POSSIBLE EXTERNAL SET TRIP POINTS AND HYSTERESIS s POWER UP/DOWN SEQUENCING s 8V, 3.3V AND 2.5V POSITIVE REGULATORS s 3.3V LOGIC COMPATIBILITY s SHOCK SENSOR DETECTOR s INTERNAL POR DELAY TIME AT POWER ON (80ms) s INTERNAL ISOFET FOR BEMF RECTIFICATION s THERMAL SHUTDOWN AND PRETHERMAL WARNING DESCRIPTION The L7200 Mozart integrates into a single chip both spindle and VCM controllers as well as power stages. The device is designed for 12V disk drive application requiring up to 2.5A of spindle and 1.7A of VCM peak currents. The device is based on the sinusoidal driving of the spindle motor. This is realized digitally by the SMOOTHDRIVETM SYSTEM. A serial port with up to 40 MHz capability provides easy interface to the microprocessor. A register controlled Frequency Locked Loop (FLL) allows flexibility in setting the spindle speed. Integrated BEMF processing, digital filter, digital masking, digital delay, and sequencing minimize the number of external components required. 1/23 September 1999 This is preliminary information on a new product now in development. Details are subject to change without notice. L7200 DESCRIPTION (continued) Power On Reset (POR) circuitry is included. Upon detection of a low voltage condition, POR is asserted, the internal registers are reset, and spindle power circuitry is tri-stated. The BEMF is rectified providing power for actuator retraction followed by dynamic spindle braking. Three Linear regulators and a Shock Sensor circuitry are also integrated. The device is built in BCD mixed signal technology allowing dense digital/analog circuitry to be combined with a high power DMOS output stage. BLOCK DIAGRAM SSBUFOUT VBOOST CHARGE PUMP SSFOUT SYSCLK BRAKE SSOUT RBIAS FCOM SSFIN SSIN PUMP SHOCK DETECTOR FLL & DIGITAL FILTER SPINDLE Architecture ISOFET PWM A VPS VCC OUT_A CTAP B A VREG3.3_IN 3.3V Regulator INDUCTIVE SENSE START-UP BIPOLAR / TRIPHASE PWM B VREG2.5_IN VREG8_DRV VREG8_IN 2.5V Regulator OUT_B OUT_C RSENSE ISENSE VCM_A+ VCC PWM C RE-SYNC C DYNAMIC/ REVERSE BRAKE 8V Regulator BEMF DETECTION A+ SDATA SCLK SDEN SERIAL PORT REGISTERS VCM PSM/LIN RAMP LOADING A- VCM CALIBRATION BEMF RECTIFICATION VCM_AVCM_GND SENSE_IN- TR_12V TR_5V TR_3.3V SUPPLY FAULT MONI T ORS THERMAL 14 BIT VCM DAC REFERENCE VOLTAGE VCC/4 & GAIN SWITCH A=4 SUPPLY SENSE_IN+ 2/23 ERROR_OUT SENSE_OUT ERROR_IN DAC_OUT GAINRES TR_2.5V PORB VDD DGND AVCC AGND GND L7200 SPINDLE SMOOTHDRIVETM ARCHITECTURE, START-UP & FLL 6bit 8bit FEED FORWARD A B PWM A BYTE TO PWM CONVERTER A/D 7bit 8bit MEMORY AND MEMORY SCAN 3x 9bit DIGITAL MULTIPLIER PWM B 9bit Resolution POWERS 10bit 10bit BIPOLAR / TRIPHASE TORQUE OPTIMIZER KFLL d REGISTER DIGITAL FILTER 12bit FLL 10bit SPIN-UP 3x 10bit 2x 12bit INDUCTIVE SENSE SERIAL PORT FREQUENCY MULTIPLIER Z.C. BEMF DETECTION PIN CONNECTION (Top view) ERROR_OUT SENSE_OUT SENSE_IN+ ERROR_IN SENSE_INSDATA DGND VREG8_DRV VREG8_IN VCM_A+ VCM_A+ VCM_GND VCM_GND VCM_AVCM_AOUT_A OUT_A RSENSE RSENSE OUT_B OUT_B RSENSE RSENSE OUT_C OUT_C 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 VCC 47 46 45 44 GND VCC VCC 43 SCLK VPS VPS 42 41 SDEN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DAC_OUT PORB VREG3.3_IN VREG3.3_DRV VREG2.5_IN VREG2.5_DRV RBIAS AVCC AGND TR_12V TR_5V TR_3.3V TR_2.5V SSIN SSBUFOUT SSFIN L7200 "MOZART" 25 24 23 22 21 20 19 18 2 VCC 3 VPS 4 VPS 5 GND 6 SYSCLK 7 FCOM 8 VDD 9 BRAKE 10 ISENSE 11 CTAP 12 GAINRES 13 VBOOST 14 PUMP 15 SSOUT 17 16 SSFOUT C PWM C 3/23 L7200 PIN FUNCTION Pin Types: D = Digital, P = Power, A = Analog N 1,2 3,4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Pin Name VCC VPS GND SYSCLK FCOM VDD BRAKE ISENSE CTAP GAINRES VBOOST PUMP SSOUT SSFOUT SSFIN SSBUFOUT SSIN TR_2.5V TR_3.3V TR_5V TR_12V AGND AVCC RBIAS +12V Power Supply after ISOFET. +12V Power Supply. Power Ground (substrate). Clock Frequency for system timers and counters Output of Spindle zero crossing or Current Sense circuit Digital +5V Supply Storage capacitor for brake circuit. Typically 5.9V Input to sense the voltage of the SPINDLE Sense Resistor. Spindle Center Tap used for Differential BEMF sensing External resistor for VCM switch gain. External main Charge Pump Capacitor (typically VCC+5.8V) External Charge Pump Shock Sensor detector Digital Output Shock Sensor detector filter Output Shock Sensor detector filter Input Shock Sensor detector amplifier Output Shock Sensor detector amplifier Input Set Point Input for 2.5V Supply monitor Set Point Input for 3.3V Supply monitor Set Point Input for 5V Supply monitor Set Point Input for 12V Supply monitor Analog Ground +12V analog Supply (after ISOFET) External resistor for setting accurate bias current Description Type P P P D D D A A A A A A D A A A A A A A A A P A A A A A A A A VREG2.5_DR 2.5V positive regulator drive output VREG2.5_IN 2.5V positive regulator sense input VREG3.3_DRV 3.3V positive regulator drive output VREG3.3_IN PORB DAC_OUT VREG8_DRV 3.3V positive regulator sense input Power On Reset Output Output of VCM DAC 8V positive regulator drive output 4/23 L7200 PIN FUNCTION (continued) N 34 35 36 37 38 39 40 41 42 43 44 45,46 47,48 49,50 51,52 53,54 55,56 57,58 59,60 61,62 63,64 Pin Name VREG8_IN SENSE_INSENSE_IN+ SENSE_OUT 8V positive regulator sense input Inverting Input of the Sense Amplifier Non inverting Input of the Sense Amplifier Output of the Sense Amplifier Description Type A A A A A A D D D D P P P A A A A A A A A ERROR_OUT Output of the Error Amplifier ERROR_IN DGND SDEN SDATA SCLK GND VPS VCC VCM_A+ VCM_GND VCM_AOUT_A RSENSE OUT_B RSENSE OUT_C Inverting Input of the Error Amplifier Digital Ground Serial Data Enable. Active high input pin for serial port enable Serial port Data input/output Serial Port Data Clock. Positive edge triggered clock input for serial data Power Ground (substrate). +12V Power Supply. +12V Power Supply after ISOFET. VCM Power Amplifier positive Output terminal. Ground for VCM power section. VCM Power Amplifier negative Output terminal. Spindle DMOS half bridge Output and Input A for BEMF sensing. Output Connection for the Motor Current Sense Resistor to ground. Spindle DMOS half bridge Output and Input B for BEMF sensing. Output Connection for the Motor Current Sense Resistor to ground. Spindle DMOS half bridge Output and Input C for BEMF sensing. ABSOLUTE MAXIMUM RATINGS Symbol Vcc Vdd Vin max Vin min SPINDLE Ipeak VCM Ipeak Maximum Supply voltage Maximum Logic supply Maximum digital input voltage Minimum digital input voltage Spindle peak sink/source output current VCM peak sink/source output current Parameter Value -0.5 to 14 -0.5 to 6 Vdd + .3 volts GND - .3 volts 2.6 1.8 Unit Volts Volts Volts Volts Amps Amps 5/23 L7200 THERMAL DATA Symbol (jc) (ja)* Ptot* Tstg,Tj Parameter Thermal resistance Junction to case Thermal resistance Junction to ambient Maximum Total Power Dissipation Maximum storage/junction temperature Value 11 40 2.0 -40 to 150 Unit C/Watt C/Watt Watt C * In typical application with multilayer 120x120mm Printed Circuit Board. RECOMMENDED OPERATING CONDITIONS Symbol Vdd Vcc Tamb Tj Supply Voltage Logic Supply Voltage Operating Ambient Temperature Junction Temperature Parameter Value 10.8 to 13.2 4.5 to 5.5 0 to 70 0 to 125 Unit V V C C ELECTRICAL CHARACTERISTCS All specifications are for 0 6/23 L7200 ELECTRICAL CHARACTERISTCS (continued) Symbol SUPPLY MONITOR VTR VHYS Ron_por TPorDly 12VTR 5VTR 3.3VTR 2.5VTR TRIP POINT 2.5V-3.3V-5V-12V HYSTERESIS VOLTAGE PORB PULL DOWN Ron POR Delay Time Minimum Voltage 12V Minimum Voltage 5V Minimum Voltage 3.3V Minimum Voltage 2.5V 8.6 4.2 3.135 2.375 INPUT RISING INPUT FALLING Vdd > 2V and sink 1mA 80 1.20 1.25 25 500 1.30 V mV W mSec V V V V Parameter Test Condition Min. Typ. Max. Unit VOLTAGE BOOST VBOOST FOSC OUTPUT VOLTAGE INTERNAL OSCILLATOR VCC+5 200 VCC+6.3 V KHz SW1 OUTPUT VIH VIL VOH VOL FSYSCLK VCM, DAC RESOLUTION DIFFERENTIAL LINEARITY 1 LSB Change - Tested - By design -1 -0.5 9 REFERENCED TO VCC/4 -5 5 5 REFERENCED TO VCC/4 -6 1 6 14 1 0.5 BITS LSB BITS mV s V % INPUT LOGIC "1" INPUT LOGIC "0" OUTPUT LOGIC "1" OUTPUT LOGIC "0" SYSTEM CLOCK ISOURCE = 20A ISOURCE = -400A 20 Vdd0.2 0.4 25 2.4 0.5 V V V V MHz INTEGRAL LINEARITY MIDSCALE OFFSET TC CONVERTION TIME FULL SCALE VOLTAGE FULL SCALE ERROR VCM, ERROR AMPLIFIER AVOL VOS OPEN LOOP GAIN INPUT OFFSET VOLTAGE DC 80 1 dB mV 7/23 L7200 ELECTRICAL CHARACTERISTCS (continued) Symbol VICM FODB Parameter INPUT COMMON MODE RANGE UNITY GAIN BANDWIDTH Test Condition Min. Typ. VCC/4 +/-1.5 10 Max. Unit V MHz VCM, POWER STAGE RDS(ON) Io IO(LEAK) Output On Resistance (Each Device) Operating Current Output Leakage Current Vcc = 14V Tj = 25C Tj = 125C 0.25 0.35 1.3 1.0 A mA VCM, CURRENT SENSE AMPLIFIER AV VICM VOCM VOS F3dB CMRR PSRR Voltage Gain Input Common Mode Range Output Common Mode Range Output Offset Voltage 3dB Bandwidth Input Common Mode Rejection Ratio Power Supply Rejection Ratio 50 60 -1mA < Io < 1mA SENSE_IN(-/+) = Vcc/4 3.88 -0.3 1.5 10 3 4 4.12 Vcc +0.3 4.5 V/V V V mV MHz dB dB VCM RETRACT Vpark Retract Voltage PKV=0 PKV=1 PKV=0 PKV=1 PKV=0 PKV=1 PKV=0 PKV=1 & PKV1=0 & PKV1=0 & PKV1=1 & PKV1=1 & PKV1=0 & PKV1=0 & PKV1=1 & PKV1=1 & RT1 = 0 & RT1 = 0 & RT1 = 1 & RT1 = 1 & PKV2=0 & PKV2=0 & PKV2=0 & PKV2=0 & PKV2=1 & PKV2=1 & PKV2=1 & PKV2=1 0.30 0.60 0.90 1.20 1.50 1.80 2.10 2.40 80 160 320 640 V Tretract Retract Time limited by the internal oscillator 200KHz RT0 = 0 RT0 = 1 RT0 = 0 RT0 = 1 ms SPINDLE, PWM CURRENT SENSE COMPARATOR TDLY Delay to Fcom Out 200 500 ns SPINDLE, POWER STAGE RDS(ON) Io IO(LEAK) Output On Resistance (each device) Start-up Current Output Leakage Current V CC = 14V Tj = 25C Tj = 125C 0.25 0.35 2 1.0 A mA 8/23 L7200 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Output Slew Rate (PWM) BEMFMI N Test Condition Reg# 2.2 = 0 Reg# 2.2 = 1 Min. Typ. 10 20 35 18 Max. Unit V/s mVp-p mV Minimum BEMF Voltage for Detection Hysteresis VHYS CURRENT SENSE AMPLIFIER Av dVo/dt Voltage Gain Output Slew Rate 3.8 4.0 20 4.2 V/V V/S 3.3V LINEAR REGULATOR V3.3 Av Ibase 3.3V Regulation Voltage Open Loop Gain Driving Base Current Iload < 0.6A 3.15 3.3 60 20 3.45 V dB mA 2.5V LINEAR REGULATOR V2.5 Av Ibase 2.5V Regulation Voltage Open Loop Gain Driving Base Current Iload < 0.6A 2.5 60 20 V dB mA 8V LINEAR REGULATOR V8 AV Ibase 8V Regulation Voltage Open Loop Gain Driving Base Current I load < 0.2A 8 60 5 V dB mA SHOCK SENSOR - INPUT OPERATIONAL AMPLIFIER A1 Av Rin FodB Open Loop Gain Input Inpedance Unity Gain Bandwidth 20 10 30 dB M KHz SHOCK SENSOR - FILTER OPERATIONAL AMPLIFIER A2 Av FodB Voffset Open Loop Gain Unity Gain Bandwidth Offset Voltage 80 5 5 dB KHz V SHOCK SENSOR - OUTPUT WINDOW COMPARATOR VH VL Vth High Vth Low Referred to Vcc/4 Referred to Vcc/4 +0.5 -0.5 V V 9/23 L7200 SERIAL PORT PARAMETER SCLK Period, (TSCK ) SCLK low time, (TCKL ) SCLK high time, (TCKH ) Enable to SCLK (TSDENS ) SCLK to disable (TSDENH ) Data set-up time before rising edge SCLK (TDS ) Data hold time (TDH ) Minimum SDEN low time (TSDENL) MIN. 25 10 10 10 12.5 5 5 30 15 TYP. MAX. UNITS ns ns ns ns ns ns ns ns Figure 1. Serial Port Timing Information SDEN SCLK SDATA 0 A0 A1 A6 D0 D1 D2 D7 1st Byte Serial Port Write Timing 2nd Byte SDEN SCLK SDATA 1 A0 A1 A6 D0 D1 D7 1st Byte Serial Port Read Timing 2nd Byte SERIAL PORT OPERATION The serial port interface is a bi-directional port for reading and writing programming data from/to the internal registers of this device. For data transfers SDEN is brought high, serial data is presented at the SDATA pin, and a serial clock is applied to the SCLK pin. After the SDEN goes high , the first 16 pulses applied to the SCLK pin will shift the data presented at the SDATA pin into an internal shift register on the rising edge of each clock. An internal counter prevents more than 16 bits from being shifted into the register. The data in the shift register is 10/23 L7200 latched after the 16th SCLK pulse. If less than 16 clock pulses are provided before SDEN goes low, the data transfer is aborted. All transfers are shifted into the serial port LSB first. The first byte of the transfer is for Address and Instruction information. The first bit is R/W instruction bit, 0 is for WRITE and 1 is for READ. Following 3 bits are for Combo Data Bank (all set to `1'). The last 4 bits are for Register Address. Figure 2. Serial Port Data Transfer Format SDEN SCLK SDATA INSTRUCTION (READ/WRITE), 1BIT ADDRESS, COMBO DATA BANK, 3 BITS ADDRESS, 4 BITS DATA, 8 BITS INTERNAL REGISTERS DEFINITION Reg: Name: Type: 0 Spindle Spin-Up Register Write only Address: 0Eh BIT 0 1 2 3 4 5 6 START EXTERNAL SEQINC STOP INDSENSE SPCOAST SPINUPTIME 0 LABEL DESCRIPTION "0" Reset and Brakes the Spindle. "1" Initiates the Spindle Start-Up procedure. "0" Spindle BEMF processing in internal mode. "1" External mode. In external mode, a "0" to "1" transition, increments the Spindle Sequencer. "0" Complete Internal Spindle Start-Up. "1" Stop after Inductive Sense "0" Normal condition. "1" in External mode, initiate the Inductive Sense "0" Spindle Outputs Enabled. "1" Disabled. Spindle Internal Spin Up. Energization Time. First Bit. 7 SPINUPTIME 1 Spindle Internal Spin Up. Energization Time. Second Bit. Bit 7 0 0 1 1 Bit 6 0 1 0 1 Time 10mS 20mS 30mS 40mS 11/23 L7200 INTERNAL REGISTERS DEFINITION (continued) Reg: Name: Type: 1 Spindle Set-Up 0 Register Write only Address: 1Eh BIT 0 1 2 SMOOTH BIPMASK MINON 0 LABEL DESCRIPTION "0" Spindle SMOOTHDRIVETM. "1" Spindle Six step drive. Spindle Mask Time. "0" 15. "1" 7.5. (Only in six step drive). Minimum ON time in Current limit. First Bit. 3 MINON 1 Minimum ON time in Current limit. Second Bit. Bit 3 0 0 1 1 4 5 BIPDELAY MASKSPIN 0 Bit 2 0 1 0 1 Min TON 6S 3S 9S 7.6S Spindle Commutation Delay. "0" 30. "1" 15. (Only in six step drive). Spindle Mask at acceleration. First Bit. Bit 6 0 0 1 1 Bit 5 0 1 0 1 Mask 3.2mS 1.6mS 0.8mS 6.4mS 6 MASKSPIN 1 Spindle Mask at acceleration. Second Bit. 7 FREEZE "0" Torque Optimizer Activated. "1" Torque Optimizer Frozen. Reg: Name: Type: 2 Spindle Set-Up 1 Register Write only Address: 2Eh BIT 0 IL0 LABEL Current Limit and Inductive Sense thresholds. First Bit. 1 IL1 Current Limit and Inductive Sense thresholds. Second Bit. DESCRIPTION Bit 1 0 0 1 1 2 3 SSLEW FLLEXT Bit 0 0 1 0 1 Vlimit 0.45V 0.50V 0.55V 0.75V Spindle Chopping Slew Rate. "0" 10V/S. "1" 20V/S. Spindle Speed control loop. "0" Internal. "1" External. 12/23 L7200 INTERNAL REGISTERS DEFINITION (continued) BIT 4 5 6 7 INDEX EXTK MECH/ELEC 8_12POLE LABEL External FLL update. "0" Spindle Speed internal KFLL. "1" All Reg#7 and Lsb of Reg#8 bits are mixed to allow external setting of KFLL. Electrical or Mechanical cycle for Spindle FLL control. "0" Mechanical. "1" Electrical. Spindle Motor Poles. "0" 8 poles. "1" 12 poles. DESCRIPTION Reg: Name: Type: 3 Spindle Set-Up 2 Register Write only Address: 3Eh BIT 0 1 2 3 4 5 6 7 ZCWINDOW REVBRAKE CLKDIV DIV1.5 FLLCOARSE<0> FLLCOARSE<1> FLLCOARSE<2> FLLCOARSE<3> LABEL DESCRIPTION Chop cycle for Spindle ZC tristate time. "0" Two. "1" One. "1" Spindle Reverse Brake. Toggling this bit will define the time before ending over normal brake. 1 = 10mS. 2 = 20mS. 3 = 40mS. SYSCLK divider. "0" SYSCLK. "1" SYSCLK divide by 2. SYSCLK divider. "0" SYSCLK. "1" SYSCLK divide by 1.5. LSB of Spindle FLL Coarse Counter. Bit 1 of Spindle FLL Coarse Counter. Bit 2 of Spindle FLL Coarse Counter. Bit 3 of Spindle FLL Coarse Counter. Reg: Name: Type: 4 Spindle FLL Coarse Register Write only Address: 4Eh BIT 0 1 2 3 4 5 LABEL FLLCOARSE<4> FLLCOARSE<5> FLLCOARSE<6> FLLCOARSE<7> FLLCOARSE<8> FLLCOARSE<9> DESCRIPTION Bit 4 of Spindle FLL Coarse Counter. Bit 5 of Spindle FLL Coarse Counter. Bit 6 of Spindle FLL Coarse Counter. Bit 7 of Spindle FLL Coarse Counter. Bit 8 of Spindle FLL Coarse Counter. Bit 9 of Spindle FLL Coarse Counter. 13/23 L7200 INTERNAL REGISTERS DEFINITION (continued) BIT 6 7 LABEL FLLCOARSE<10> FLLCOARSE<11> DESCRIPTION Bit 10 of Spindle FLL Coarse Counter. MSB of Spindle FLL Coarse Counter. Reg: Name: Type: 5 Spindle FLL Fine Register Write only Address: 5Eh BIT 0 1 2 3 4 5 6 7 FLLFINE<0> FLLFINE<1> FLLFINE<2> FLLFINE<3> FLLFINE<4> FLLFINE<5> FLLFINE<6> FLLFINE<7> LABEL DESCRIPTION LSB of Spindle FLL Fine Counter. Bit 1 of Spindle FLL Fine Counter. Bit 2 of Spindle FLL Fine Counter. Bit 3 of Spindle FLL Fine Counter. Bit 4 of Spindle FLL Fine Counter. Bit 5 of Spindle FLL Fine Counter. Bit 6 of Spindle FLL Fine Counter. Bit 7 of Spindle FLL Fine Counter. Reg: Name: Type: 6 Spindle Set-Up 3 Register Write only Address: 6Eh BIT 0 1 2 3 4 5 6 7 FLLFINE<8> FLLFINE<9> FLLFINE<10> COEFF_B0<8> COEFF_B1<8> STUCKSET CLAMP0 CLAMP1 LABEL DESCRIPTION Bit 8 of Spindle FLL Fine Counter. Bit 9 of Spindle FLL Fine Counter. MSB of Spindle FLL Fine Counter. MSB of Spindle FLL filter coefficient B0. MSB of Spindle FLL filter coefficient B1. Spindle Stuck Rotor Time. "0" 400mS. "1" 100mS. KFLL clamp. First Bit. KFLL clamp. Second Bit. Bit 7 0 0 1 1 Bit 6 0 1 0 1 Clamp 0.50 0.55 0.60 0.65 14/23 L7200 INTERNAL REGISTERS DEFINITION (continued) Reg: Name: Type: 7 Spindle FLL Filter Coefficient A1 Register Write only Address: 7Eh BIT 0 1 2 3 4 5 6 7 LABEL COEFF_A1<0> COEFF_A1<1> COEFF_A1<2> COEFF_A1<3> COEFF_A1<4> COEFF_A1<5> COEFF_A1<6> COEFF_A1<7> DESCRIPTION LSB of Spindle FLL filter coefficient A1. Bit 1 of Spindle FLL filter coefficient A1. Bit 2 of Spindle FLL filter coefficient A1. Bit 3 of Spindle FLL filter coefficient A1. Bit 4 of Spindle FLL filter coefficient A1. Bit 5 of Spindle FLL filter coefficient A1. Bit 6 of Spindle FLL filter coefficient A1. MSB of Spindle FLL filter coefficient A1. Reg: Name: Type: 8 Spindle FLL Filter Coefficient B0 Register Write only Address: 8Eh BIT 0 1 2 3 4 5 6 7 LABEL COEFF_B0<0> COEFF_B0<1> COEFF_B0<2> COEFF_B0<3> COEFF_B0<4> COEFF_B0<5> COEFF_B0<6> COEFF_B0<7> DESCRIPTION LSB of Spindle FLL filter coefficient B0. Bit 1 of Spindle FLL filter coefficient B0. Bit 2 of Spindle FLL filter coefficient B0. Bit 3 of Spindle FLL filter coefficient B0. Bit 4 of Spindle FLL filter coefficient B0. Bit 5 of Spindle FLL filter coefficient B0. Bit 6 of Spindle FLL filter coefficient B0. Bit 7 of Spindle FLL filter coefficient B0. 15/23 L7200 INTERNAL REGISTERS DEFINITION (continued) Reg: Name: Type: 9 Spindle FLL Filter Coefficient B1 Register Write only Address: 9Eh BIT 0 1 2 3 4 5 6 7 LABEL COEFF_B1<0> COEFF_B1<1> COEFF_B1<2> COEFF_B1<3> COEFF_B1<4> COEFF_B1<5> COEFF_B1<6> COEFF_B1<7> DESCRIPTION LSB of Spindle FLL filter coefficient B1. Bit 1 of Spindle FLL filter coefficient B1. Bit 2 of Spindle FLL filter coefficient B1. Bit 3 of Spindle FLL filter coefficient B1. Bit 4 of Spindle FLL filter coefficient B1. Bit 5 of Spindle FLL filter coefficient B1. Bit 6 of Spindle FLL filter coefficient B1. Bit 7 of Spindle FLL filter coefficient B1. Reg: Name: Type: 10 Voice Coil DAC 0 Register Write only Address: AEh BIT 0 1 2 3 4 5 6 7 LABEL VCMDAC<0> VCMDAC<1> VCMDAC<2> VCMDAC<3> VCMDAC<4> VCMDAC<5> VCMDAC<6> VCMDAC<7> LSB of Voice Coil DAC. Bit 1 of Voice Coil DAC. Bit 2 of Voice Coil DAC. Bit 3 of Voice Coil DAC. Bit 4 of Voice Coil DAC. Bit 5 of Voice Coil DAC. Bit 6 of Voice Coil DAC. Bit 7 of Voice Coil DAC. DESCRIPTION 16/23 L7200 INTERNAL REGISTERS DEFINITION (continued) Reg: Name: Type: 11 Voice Coil DAC 1 Register Write only Address: BEh BIT 0 1 2 3 4 5 6 7 LABEL VCMDAC<8> VCMDAC<9> VCMDAC<10> VCMDAC<11> VCMDAC<12> VCMDAC<13> PSM/LIN VCMEN Bit 8 of Voice Coil DAC. Bit 9 of Voice Coil DAC. Bit 10 of Voice Coil DAC. Bit 11 of Voice Coil DAC. Bit 12 of Voice Coil DAC. MSB of Voice Coil DAC. VCM Current control. "0" Linear mode. "1" PSM mode. "0" VCM Disabled. "1" VCM Enabled. DESCRIPTION Reg: Name: Type: 12 Voice Coil Retract Register Write only Address: CEh BIT 0 1 2 PKV0 PKV1 PKV2 LABEL Retract Voltage. First Bit. Retract Voltage. Second Bit. Retract Voltage. Third Bit. DESCRIPTION Bit 2 0 0 0 0 1 1 1 1 3 4 RT0 RT1 Retract Time. First Bit. Retract Time. Second Bit. Bit 4 0 0 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 Bit 3 0 1 0 1 Voltage 0.30V 0.60V 0.90V 1.20V 1.50V 1.80V 2.10V 2.40V Time 80ms 160ms 320ms 640ms 17/23 L7200 INTERNAL REGISTERS DEFINITION (continued) BIT 5 6 7 RETDIR RETRACT RETBRK LABEL DESCRIPTION Retract Direction. "0" VCM- high, VCM+ low. "1" VCM- low, VCM+ high. "1" Retracts the Voice Coil arm. "1" Brakes the VCM for the first 20mS of the retract time then it reverses the direction of the retract opposite to the RETDIR bit setting for other 20mS, then it finish the normal retract. This total 40mS are subtructed from the programmed Retract time. Reg: Name: Type: 13 Voice Coil Set-Up and Ramp Loading Register Write only Address: DEh BIT 0 1 2 3 LABEL VCMCAL0 VCMCAL1 VCMCAL2 VCMCAL3 VCM Calibration. First Bit. VCM Calibration. Second Bit. VCM Calibration. Third Bit. VCM Calibration. Fourth Bit. DESCRIPTION Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 4 5 6 7 VCMCALDIR RAMPLOADING SAMPLE/HOLD TRISTATE Bit2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Adj None 1.4mV 2.8mV 4.2mV 5.6mV 7.0mV 8.4mV 9.8mV 11.2mV 12.6mV 14.0mV 15.4mV 16.8mV 18.2mV 19.6mV 21.0mV VCM Calibration Direction. "0" Positive offset. "1" Negative offset. VCM Ramp Loading Setting. "1" Ramp Loading mode. VCM Ramp Loading Setting. "0" Hold. "1" Sampling. VCM Ramp Loading Setting. "1" Synchronusly clamps the VCM outputs until current is less than 100mA, then tristate them. 18/23 L7200 INTERNAL REGISTERS DEFINITION (continued) Reg: Name: Type: 14 System FunctionSet-Up Register Write only Address: EEh BIT 0 1 2 3 4 5 6 7 LABEL GAINSWITCH EXTP EXTN EXTVCM VBDIS SHOCKEN DESCRIPTION VCM current loop Gain Switch. "0" Switch open. "1" Switch close. VCM external mode VCMP output. "0" VCMP low. "1" VCMP high. VCM external mode VCMN output. "0" VCMN low. "1" VCMN high. VCM mode. "0" Internal. "1" External. Vboost oscillatotor. "0" Enabled. "1" Disabled. Schock Detector. "0" Disabled. "1" Enabled. Reg: Name: Type: 15 Spindle Diagnostic Register Read only Address: 0Fh BIT 0 1 2 3 4 5 6 7 LOCK NOTHR PHREADY STUCKROTOR PHASE<0> PHASE<1> PHASE<2> BACKSPIN LABEL DESCRIPTION "0" Indicates Spindle Speed error (>16S sample, either mechanical or electrical). "1" Indicates that the Inductive Sense threshold is not reached. "1" Indicates that the Phase reading of the motor succeded. "1" Indicates that the Spindle BEMF is not detected. Inductive Sense Phase detected. First Bit. Inductive Sense Phase detected. Second Bit. Inductive Sense Phase detected. Third Bit. "1" Indicateds a Back rotation of the Spindle Motor. 19/23 L7200 INTERNAL REGISTERS DEFINITION (continued) Reg: Name: Type: 16 System Diagnostic Register Read only Address: 1Fh BIT 0 1 2 3 4 5 LABEL PHASEFINE<0> PHASEFINE<1> PHASEFINE<2> PHASEFINE<3> THWARNING THSHUTDOWN DESCRIPTION Torque Optimizer Phase Shift. First Bit. Torque Optimizer Phase Shift. Second Bit. Torque Optimizer Phase Shift. Third Bit. Torque Optimizer Phase Shift. Fourth Bit. Thermal Warning. "1" Indicates that the Device temperature is approximately 25C lower than the thermal shutdown's one. Thermal Shutdown. "1" Indicates that the Device temperature has exceeded 160C. The bit will reset (=0) when the temperature drops below 130C. Outputs of the Calibration Comparator. "1" Indicates that the Voicel Coil is Retracting. 6 7 VCMCAL RET Reg: Name: Type: 17 ID Register Read only Address: 2Fh BIT 0 1 2 3 4 5 6 7 ID_REV0 ID_REV1 ID_REV2 ID_REV3 ID_REV4 ID_REV5 ID_REV6 ID_REV7 LABEL DESCRIPTION Device Minor Revision. First Bit. Device Minor Revision. Second Bit. Device Minor Revision. Third Bit. Device Minor Revision. Fourth Bit. Device Major Revision. First Bit. Device Major Revision. Second Bit. Device Major Revision. Third Bit. Device Major Revision. Fourth Bit. 20/23 L7200 APPLICATION CIRCUIT OUT_A OUT_B OUT_C CTAP 0.3ohm / 1W 2.2uF 5V 24 44 56 55 60 59 64 63 11 62 61 58 RSENSE OUT_B OUT_B OUT_A BRAKE OUT_A OUT_C OUT_C CTAP RSENSE RSENSE RSENSE AGND GND GND VDD 57 9 8 5 12V 10 33 PNP 34 10uF 3 4 29 PNP 30 10uF 46 45 27 PNP 28 10uF 12 32 39 38 62K 37 1nF 10K 12K 60K 12V 5V 12V 5V 25 1 VCC 22uF/25V Tantalum + 2 47 48 40 SYSCLK SDEN SDATA SCLK FCOM PORB SENSOR OUT SENSOR IN 33nF 10K 6 41 42 43 7 31 15 19 18 17 330pF AVCC VCC VCC VCC VCC DGND SYSCLK SDEN SDATA SCLK FCOM PORB SSOUT SSIN SENSE_IN+ SSBUFOUT VBOOST SSFOUT VCM_AVCM_ASSFIN SENSE_INVCM_GND VCM_GND ISENSE VREG8_DRV VREG8_IN VPS VPS VREG3.3_DRV "MOZART" TQFP64 VREG3.3_IN VPS VPS VREG2.5_DRV VREG2.5_IN GAINRES DAC_OUT ERROR_IN ERROR_OUT VCM_A+ VCM_A+ TR_3.3V TR_2.5V 20 TR_12V SENSE_OUT RBIAS 26 21.5K 16 13 14 51 52 53 54 35 36 49 50 23 22 TR_5V PUMP 100K 1N4148 47nF 1uF 1N4148 VCC VCM_A- VCM_A+ 0.25ohm 1W Analog Ground Power Ground VCM Ground 21 Digital Ground 21/23 L7200 DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12 mm TYP. MAX. 1.60 0.15 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0(min.), 7(max.) 0.75 1.45 0.28 0.20 0.002 0.053 0.007 MIN. inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011 OUTLINE AND MECHANICAL DATA 0.0047 0.0063 0.0079 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0157 0.0236 0.0295 0.0393 TQFP64 D D1 A D3 A1 48 49 33 32 0.10mm Seating Plane A2 B E3 E1 64 1 e 16 17 C L1 E L K TQFP64 22/23 B L7200 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 23/23 |
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